THEORY
schedule25 min

Why HDL is NOT Programming

The fundamental paradigm shift from software to hardware thinking

The Fundamental Truth

If you're coming from software development, prepare to completely rewire your brain. HDL (Hardware Description Language) is NOT programming. This is the single most important mental shift you must make before writing a single line of code.

In software, you write instructions that tell a CPU what to do step-by-step. The CPU fetches each instruction, decodes it, executes it, and moves to the next one. This is the Von Neumann architecture - sequential, predictable, comfortable.

HDL is different. You're not writing instructions. You're describing PHYSICAL CIRCUITS made of transistors, wires, and logic gates. These circuits exist in space, consume power, and operate simultaneously. Your Tang Primer 20K has 20,736 logic cells - all working in parallel, all the time.

warningReality Check

Most beginners fail at FPGAs because they try to "program" them like software. They write Verilog like it's C code and wonder why nothing works. Don't be that person.

The Wrong Mental Model (Software Thinking)

Let's start with what you know - software. Here's a simple Python program:

codePYTHON
# Software: Sequential execution
a = 5
b = 10
c = a + b
print(c)  # Output: 15

# Now change a
a = 20
print(c)  # Output: STILL 15!

What happened? The variable c was calculated ONCE and stored. When a changed, c didn't automatically update because that's not how software works.

To update c, you'd need to execute the addition statement again:

codePYTHON
a = 20
c = a + b  # Explicitly recalculate
print(c)  # Now it's 30

This is sequential thinking: variables store values, operations happen in order, you control when things execute.

The Correct Mental Model (Hardware Thinking)

Now let's think in hardware. Here's the equivalent Verilog code:

codeVERILOG
// Hardware: Describing physical circuits
wire [3:0] a;
wire [3:0] b;
wire [3:0] c;

assign c = a + b;  // This creates a physical adder circuit!

What's different? EVERYTHING.

  • Wires, not variables: a, b, and c aren't memory locations - they're physical wires carrying electrical signals.
  • assign creates hardware: The assign statement doesn't "execute" - it describes a permanent circuit connection. The FPGA synthesis tool reads this and instantiates a 4-bit adder circuit made of logic gates.
  • Always connected: When a or b changes, c updates AUTOMATICALLY within nanoseconds because they're physically wired together through the adder.
  • No CPU needed: There's no processor fetching instructions. The circuit just... exists. Signals flow through it continuously at the speed of light (well, almost).
lightbulbThe Light Switch Analogy

Think about a light switch in your house. When you flip it, the light turns on immediately. You don't need to "run a program" to make electricity flow from the switch to the bulb - they're physically wired together. That's how HDL works. You're building circuits, not writing programs.

Software vs Hardware: Side-by-Side

Software (Programming)Hardware (HDL)
Variables store values in memoryWires carry electrical signals
Code executes line by lineAll circuits operate simultaneously
Functions are reusable code blocksModules are physical components
if statements control execution flowif statements describe multiplexers
Timing depends on CPU clock speed (GHz)Timing depends on wire delays (nanoseconds)
Performance limited by sequential bottleneckPerformance limited by area and routing

What Actually Happens Inside the FPGA

Let's trace what happens when you write this simple Verilog code and load it onto your Tang Primer 20K:

codeVERILOG
module simple_and (
    input  wire a,
    input  wire b,
    output wire y
);
    assign y = a & b;
endmodule

Step 1: Synthesis (Building the Circuit)

The Gowin EDA tool reads your code and performs "synthesis" - converting your HDL description into actual digital logic. For this AND gate:

  • 1.It identifies that you need 2 input pins, 1 output pin, and 1 AND gate
  • 2.It allocates one LUT (Look-Up Table) - the fundamental building block of your FPGA
  • 3.It programs the LUT to implement the AND truth table

Step 2: Place & Route (Physical Layout)

Now the tool decides WHERE on the physical chip to place your circuit:

  • 1.Picks a specific LUT location from the 20,736 available
  • 2.Routes physical wires (metal traces inside the silicon) from input pins to the LUT
  • 3.Routes wires from the LUT output to the output pin

Step 3: Bitstream Generation (Programming File)

The tool creates a binary file (bitstream) that configures your FPGA:

  • 1.Programs the LUT with the AND truth table values
  • 2.Configures routing switches to connect the wires
  • 3.Sets pin directions (input/output) and electrical properties

Step 4: Runtime (Circuit in Action)

Once loaded onto the FPGA, your circuit just... works:

  • 1.Input signals flow from pins through wires to the LUT
  • 2.The LUT instantly outputs the correct value based on its programmed truth table
  • 3.Output signal flows through wires to the output pin
  • 4.Total delay: ~5-10 nanoseconds (propagation delay through LUT and wires)
flash_onThe Power of Hardware

This AND gate responds in NANOSECONDS. No operating system overhead, no context switching, no CPU instruction fetching. Just pure, dedicated hardware. That's why FPGAs are used in high-frequency trading, radar systems, and data centers - they're FAST.

Understanding 'assign': The Most Important Keyword

In Verilog, assign is your primary tool for describing combinational logic (circuits without memory). It creates permanent wire connections.

codeVERILOG
wire [7:0] input_a;
wire [7:0] input_b;
wire [7:0] sum;
wire [7:0] difference;
wire [7:0] bitwise_and;

// Each assign statement describes a separate physical circuit
assign sum = input_a + input_b;           // 8-bit adder circuit
assign difference = input_a - input_b;    // 8-bit subtractor circuit
assign bitwise_and = input_a & input_b;   // 8 AND gates (one per bit)

Critical insight: All three circuits exist SIMULTANEOUSLY and operate IN PARALLEL. When input_a or input_b changes:

  • sum updates through the adder
  • difference updates through the subtractor
  • bitwise_and updates through the AND gates

All at the same time. No waiting, no scheduling, no thread management. Just physics.

Key Takeaways

1. HDL Describes Circuits, Not Algorithms

You're not telling a computer what steps to execute. You're describing what physical components exist and how they're connected.

2. Everything Happens Simultaneously

All your assign statements create separate circuits that operate in parallel. There's no "first" or "last" - they all work at once.

3. Wires, Not Variables

Wires don't "store" values - they continuously carry whatever signal is driving them. Think electrical current, not memory addresses.

4. Synthesis Converts HDL to Silicon

The synthesis tool reads your code and figures out what actual physical hardware to build. Good HDL makes this process efficient.

What's Next

Now that you understand the fundamental paradigm shift, we'll dive deeper into:

  • How parallelism actually works in FPGAs
  • The difference between combinational and sequential logic
  • Why clocks are needed for sequential circuits
  • Writing your first actual HDL module

Take a break. Let this sink in. This mental model is THE foundation of everything else you'll learn. If you don't get this right, you'll struggle with every lesson that follows.