RISC-V Soft Core + Rust

Your masterpiece. Instantiate a RISC-V soft processor core on your FPGA, compile Rust code to run on it, and watch your custom silicon execute your custom software. This is the pinnacle - you control the entire stack from gates to high-level code.

scheduleTime

20+ hours including toolchain setup and debugging

bar_chartDifficulty

Expert

codeCode

~800 lines Verilog + 200 lines Rust

schoolWhat You'll Learn

check_circleCPU architecture and instruction sets
check_circleInstantiating pre-built IP cores (RISC-V)
check_circleMemory mapping and address decoding
check_circleCross-compiling Rust for custom targets
check_circleBootloader and firmware loading
check_circleHardware-software codesign

constructionWhat You'll Build

build_circleComplete RISC-V SoC (System on Chip)
build_circleMemory-mapped peripherals (UART, GPIO, timers)
build_circleRust firmware running on your CPU
build_circleA simple operating system kernel
build_circleBlink LEDs from Rust code running on your FPGA
build_circleThe ultimate embedded systems achievement

settingsTechnical Details

Modules

riscv_top.vmemory_controller.vperipheral_bus.vuart_peripheral.v

Key Concepts

CPU instantiationAXI/Wishbone busesMemory mapsRust no_stdCross-compilationLinker scripts

Synthesis

32-bit RISC-V core @ 50MHz with 32KB RAM

publicReal World Application

This is how commercial FPGAs are used: instantiating soft cores like Xilinx's MicroBlaze or Intel's Nios II. You're using the same workflow that designs chips for satellites, medical devices, and aerospace systems. This is professional-level FPGA design.

checklistPrerequisites

arrow_rightAll previous weeks completed
arrow_rightRust fundamentals
arrow_rightUnderstanding of CPU architecture
arrow_rightComfortable with complex systems

arrow_forwardNext Steps

After this, you're ready for professional FPGA work. You understand the full stack from gates to software. Congratulations - you've mastered FPGAs.